k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary 4mx16 revision 0.6 november 2001 sdram 52csp (v dd /v ddq 3.0v/3.0v & 3.3v/3.3v)
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary revision history revision 0.0 (february 21. 2001, target) ? first generation of 64mb mobile sdram (v dd 3.0v, v ddq 3.0v). revision 0.1 (april 21. 2001, target) ? addition of extended temperature(-25?c ~ 85?c) specification. ? changed trcd and trp of -75 part from 22.5ns to 20ns, in order to cover 100mhz, 2-2-2 characteristics of 133mhz, 3-3-3 part. revision 0.2 (june 20. 2001, target) ? changed device name from low power sdram to mobile sdram. revision 0.3 (august 1. 2001, preliminary) ? integration to k4s641633f-gxxx of 3.0v and 3.3v part. ? changed of tsac from 6ns to 6.5ns in case of -1l part, from 7ns to 7.5ns in case of -15 part. ? changed of toh from 3ns to 2.5ns. ? changed v ih min. from 2.0 v to 0.8xv ddq and v oh min. from 2.4v to 0.9xv ddq. revision 0.4 (october 10. 2001, preliminary) ? generation of -1h(100mhz, cl2) bin and deleting of -15(66mhz, cl2) bin. ? changed of cl2 tsac from 6ns to 7ns for -75 part, cl3 tsac from 6ns to 7ns and cl2 tsac from 6ns to 8ns and cl1 tsac from 18ns to 20ns for -1l part. ? changed of toh from 3ns to 2.5ns. ? changed of tss from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1l part. ? changed v ih min. from 0.8xv ddq to0.9xv ddq and v oh min. from 0.9xv ddq to0.95xv ddq . ? changed i oh from -0.1ma to-2ma and i ol from 0.1ma to2ma. ? changed commercial temperature range from 0 c ~ 70 c to -25 c ~ 70 c. ? changed self refresh current. revision 0.5 (october 12. 2001, preliminary) ? changed vih min. from 0.9xvddq to 2.0v and voh min. from 0.95xvddq to 2.4v. ? changed vil max. from 0.3v to 0.8v and vol min. from 0.2v to 0.4v. revision 0.6 (november 7. 2001, preliminary) ? changed vih min. from 2.0v to 2.2v and vil max. from 0.8v to 0.5v.
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary the k4s641633f is 67,108,864 bits synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 16 bits, fabricated with samsung?s high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. ? 3.0v power supply. ? lvttl compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (1 & 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation. ? dqm for masking. ? auto refresh. ? 64ms refresh period (4k cycle). ? commercial temperature operation (-25 c ~ 70 c). extended temperature operation (-25 c ~ 85 c). ? 52balls csp. general description features 1m x 16bit x 4 banks sdram in 52csp * samsung electronics reserves the right to change products or specification without notice. bank select data input register 1m x 16 1m x 16 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we l(u)dqm lwe ldqm dqi clk add lcas lwcbr 1m x 16 1m x 16 timing register functional block diagram ordering information part no. max freq. interface package k4s641633f-gl/n75 133mhz(cl=3) 100mhz(cl=2) lvttl 52 csp k4s641633f-gl/n1h 100mhz(cl=2) k4s641633f-gl/n1l 100mhz(cl=3) *1 -gl ; low power, operating temperature ; -25 c ~ 70 c. -gn ; low power, operating temperature ; -25 c ~ 85 c. 1. in case of 40mhz frequency, cl1 can be supported. note :
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary symbol min typ max a 0.90 0.95 1.00 a 1 - 0.35 - e - 6.60 - e 1 - 3.75 - d - 11.00 - d 1 - 9.0 - e - 0.75 - b 0.40 0.45 0.5 z - - 0.08 f e d c b n l j h g 52ball(4x13) csp 1 2 5 6 a vss dq15 dq0 v dd b dq14 v ssq v ddq dq1 c dq13 v ddq v ssq dq2 d dq12 dq11 dq4 dq3 e dq10 v ssq v ddq dq5 f dq9 v ddq v ssq dq6 g dq8 v dd vss dq7 h clk udqm ldqm we j cke cs ras cas k a11 a9 ba1 ba0 l a8 a7 a0 a10 m a6 a5 a2 a1 n vss a4 a3 v dd pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 11 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable l(u)dqm data input/output mask dq 0 ~ 15 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground a package dimension and pin configuration m k < bottom view *1 > e 1 5 2 1 6 3 4 e d 1 d d / 2 e e/2 #a1 ball origin indicator k 4 s 6 4 1 6 3 3 f - g s a m s u n g < top view *2 > < top view *2 > w e e k a a1 j b z *1: bottom view *2: top view [unit:mm] max. 0.20 encapsulant
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter symbol min typ max unit note supply voltage v dd 2.7 3.0 3.6 v v ddq 2.7 3.0 3.6 v input logic high voltage v ih 2.2 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.5 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 capacitance (v dd = 3.0v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 2.0 4.0 pf ras , cas , we , cs , cke, dqm c in 2.0 4.0 pf address c add 2.0 4.0 pf dq 0 ~ dq 15 c out 3.5 6.0 pf 1. v ih (max) = 5.3v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. note : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note :
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a =-25 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter symbol test condition version unit note -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 60 55 55 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.5 ma i cc2 ps cke & clk v il (max), t cc = 0.5 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 11 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 8 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 5 ma i cc3 ps cke & clk v il (max), t cc = 5 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 22 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 22 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 90 70 70 ma 1 refresh current i cc5 t rc 3 t rc (min) 135 120 120 ma 2 self refresh current i cc6 cke 0.2v -gl 400 ua 3 -gn ua 4 1. measured with outputs open. 2. refresh period is 64ms. 3. k4s641633f-gl** 4. k4s641633f-gn** 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq) notes :
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note - 75 -1h -1l row active to row active delay t rrd (min) 15 20 20 ns 1 ras to cas delay t rcd (min) 20 20 24 ns 1 row precharge time t rp (min) 20 20 24 ns 1 row active time t ras (min) 45 50 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 70 84 ns 1 last data in to row precharge t rdl (min) 2 clk 2 last data in to active delay t dal (min) 2 clk + trp - last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 cas latency=1 - 0 ac operating test conditions (v dd = 2.7v ~ 3.6v , t a =-25 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter value unit ac input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see fig. 2 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes : v ddq 1200 w 870 w output 30pf v oh (dc) = 2.4v , i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 0.5 x vddq 50 w output 30pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol - 75 -1h -1l unit note min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 10 10 12 cas latency=1 - - 25 clk to valid output delay cas latency=3 t sac 5.4 7 7 ns 1,2 cas latency=2 7 7 8 cas latency=1 - - 20 output data hold time cas latency=3 t oh 2.5 2.5 2.5 ns 2 cas latency=2 2.5 2.5 2.5 cas latency=1 - - 2.5 clk high pulse width t ch 2.5 3 3 ns 3 clk low pulse width t cl 2.5 3 3 ns 3 input setup time t ss 2.0 2.5 2.5 ns 3 input hold time t sh 1.0 1.5 1.5 ns 3 clk to output in low-z t slz 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 7 7 ns cas latency=2 7 7 8 cas latency=1 - - 20
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the assoiated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) note :
k4s641633f-gl(n) rev. 0.6 nov. 2001 cmos sdram preliminary normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved full page length : 256(x16) mode register field table to program modes register programmed with normal mrs address ba0 ~ ba1 *1 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu w.b.l test mode cas latency bt burtst length 1. apply power and start clock, attempt to maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. power is applied to vdd and vddq (simultaneously). 3. maintain stable power, stable clock and nop input condition for a minimum of 200us. 4. issue precharge commands for all banks of the devices. 5. issue 2 or more auto-refresh commands. 6. issue a mode register set command to initialize the mode register. note : 1. in order to assert normal mrs, ba0 and ba1 should set "0" absolutely. power up sequence
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